In recent advancement of digital technologies in electronic hardware, larger-capacity and nonvolatile semiconductor memory apparatuses have been vigorously developed in order to store data of music, images, information and so on. For example, nonvolatile semiconductor memory apparatuses using ferroelectric substances as capacitive elements are now used in various fields. However, the ferroelectric substances in a film state have very small residual polarization values and therefore require thermal treatment in an oxygen atmosphere to improve a hysteresis characteristic. In the thermal treatment, metal wires in a wire forming region provided under the ferroelectric substance is oxidized by oxygen diffusing through an interlayer insulating layer, causing a problem in achievement of further miniaturization and higher density in the future.
Under the circumstances, a nonvolatile semiconductor memory apparatus is disclosed, which is manufactured by a manufacturing method including a step for forming an anti-oxidation film after forming a metal wire in an uppermost layer in a wire forming region in which a multi-layer wire layer is formed, a step for forming a ferroelectric substance after forming the anti-oxidation film, and a step for performing thermal treatment in an oxygen atmosphere after forming the ferroelectric substance (see patent document 1).
FIG. 14 is a cross-sectional view of a nonvolatile semiconductor memory apparatus using the ferroelectric substance illustrated in this example as a memory portion. As shown in FIG. 14, transistors 72 each of which is comprised of a source region 72a, a drain region 72b, a gate insulating film 72c and a gate electrode 72d are provided on a semiconductor substrate 71. First electrode wires 73a are provided on a first interlayer insulating layer 74a and connected to transistors 72 via their associated through-conductors 75a, respectively.
In this case, the electrode wires are formed in a multi-layer form. On the first electrode wire 73a, a second interlayer insulating layer 74b, a second electrode wire 73b, and a third interlayer insulating layer 74c are sequentially provided. In addition, on the third interlayer insulating layer 74c, an anti-oxidation film 76 and a fourth interlayer insulating layer 74d are provided. Further, in specified regions on the fourth interlayer insulating layer 74d, ferroelectric capacitors 80 each including a lower electrode 77, a ferroelectric film 78 and an upper electrode 79 are provided. A metal wire 82 connected with the upper electrode 79 of each ferroelectric capacitor 80 is provided with the second interlayer insulating layer 81 interposed therebetween.
The ferroelectric capacitor 80 is entirely subjected to thermal treatment in an oxygen atmosphere after formation. The anti-oxidation film 76 serves to prevent the oxidation of the electrode wires formed under the ferroelectric capacitor 80 by the thermal treatment in such an oxygen atmosphere. However, the lower electrode wires 77 of the ferroelectric capacitors 80 are connected to the second electrode wires 73b via the through-conductors 75c, while the through-conductors 75c are provided to penetrate through the anti-oxidation film 76 immediately under the ferroelectric capacitors 80. Therefore, the anti-oxidation film 76 has a structure separated by these through-conductors 75c and is relatively difficult to provide a sufficient oxygen blocking property.
Furthermore, in contrast to the nonvolatile memory apparatus using the ferroelectric capacitors, in recent years, a nonvolatile semiconductor memory apparatus (hereinafter referred to as ReRAM) using a material whose resistance value changes according to electric pulses applied and continues to keep its state has attracted an attention because it can easily have compatibility with a normal semiconductor process.
For example, there is disclosed an apparatus configuration, for enabling the use of the existing DRAM step as it is, in a ReRAM including one transistor and one memory portion. The ReRAM includes transistors and nonvolatile memory portions connected to drains of the transistors. The memory portion has a structure in which a resistance variable layer whose resistance reversibly changes according to current pulses applied is sandwiched between an upper electrode and a lower electrode. As the resistance variable layer, a nickel oxide layer (NiO), a vanadium oxide layer (V2O5), a zinc oxide layer (ZnO), a niobium oxide layer (Nb2O5), a titanium oxide layer (TiO2), a tungsten oxide layer (WO3), a cobalt oxide layer (CoO), etc is used. It is known that the transition metal oxide is allowed to have a specified resistance value by application of a voltage or current having a threshold or higher and to hold its resistance value until the transition metal oxide is newly applied with a voltage or current. And the transition metal oxide can be manufactured using the existing DRAM step as it is (e.g., patent document 2).
The second example includes one transistor and one nonvolatile memory portion. Also, a cross-point type nonvolatile semiconductor memory apparatus using a perovskite structure material is also disclosed (see, e.g., patent document 3). This nonvolatile memory apparatus has a structure in which stripe-shaped lower electrodes are provided on a substrate and an active layer is provided so as to cover the entire surface of the lower electrodes. As the active layer, a resistance variable layer whose resistance reversibly changes according to electric pulses is used. On the active layer, stripe-shaped upper electrodes are provided to respectively cross the lower electrodes at a right angle. A region where each of the lower electrodes and each of the upper electrodes cross each other such that the active layer is sandwiched between the lower electrode and the upper electrode forms a memory portion. The lower electrodes and the upper electrodes serve as word lines or bit lines. With such a cross-point configuration, a larger capacity is attainable.    Patent document 1: Japanese Laid-Open Patent Application Publication No. 2001-217397    Patent document 2: Japanese Laid-Open Patent Application Publication No. 2004-363604    Patent document 3: Japanese Laid-Open Patent Application Publication No. 2003-68984